Electronic Design

Test Software Now Generates SystemC Code

In its latest incarnation, TestBencher Pro supports graphical code generation for the SystemC language. Version 7.2 of TestBencher Pro provides users with a graphical environment for generating ...
EDN

Recycle RTL test benches to verify Transaction-Level IP Models

System architects working on system-on-chip (SoC) designs are hampered by the dearth of reliable ways to evaluate an architecture or verify hardware and software together. Fortunately, SystemC, an ...
Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...