Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...
EDN

Additional structures in analog layout beyond schematic

A schematic diagram is not a detailed blueprint of an analog circuit; instead, it’s more like architectural sketch of the circuit. Look at any schematic for a CMOS analog IC circuit and you will see ...
Semiconductor Engineering

Mobility Gets A Boost With Expanded Epi Applications

Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of ...
Semiconductor Engineering

Speeding Up NMOS

For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...
EDN

Low Power LDO Design Techniques for Really Small Profile Applications, Part 2

In our previous post Low Power LDO Design Techniques for Really Small Profile Applications, Part 1, we reviewed LDO design tradeoffs using an NMOS pass transistor. This design approach is proven good ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...